The actively updated and publicly visible project home page of CXL SIG is here. In that open forum with current¹ (and future², hopefully) CRSS members, we are exploring software and system architecture evolution around the trend of Memory Disaggregation.

• Why CXL and Disaggregation?

• Microarchitecture Co-evolution with CXL (ISAs, Caches, Near-

• Linux HMM scope, co-evolution with CXL, and limitations

¹From the current membership, Intel is active. Facebook/Meta's Manoj led the discussion on CXL at the last IAB, with Samsung, Hynix, and Marvell actively participating.

²We invite Rambus, Amazon, and other companies taking advantage of CXL SIG to join CRSS -- an NSF-funded I/UCRC (the I stands for Industry) -- as member companies ahead of our November.

Current Stage

• Survey and Research Problem Definition
• Tracking industry developments and emerging requirements with industry participants

Next Up

• Measurement, Modeling and Simulation of Workloads and Systems with Disaggregated Memory